HD6417705F133V Datasheet, PDF (223/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name
31 to 21 
Initial
Value R/W
0
R
20
A2ROW1 0
R/W
19
A2ROW0 0
R/W
18

0
R
17
A2COL1 0
R/W
16
A2COL0 0
R/W
15 to 13 
0
R
12
SLOW 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Bits of Row Address for Area 2
Specifies the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Setting prohibited
Reserved
This bit is always read as 0. The write value should always be
0.
Number of Bits of Column Address for Area 2
Specifies the number of bits of column address for area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value should
always be 0.
Low-Frequency Mode
Specifies the output timing of command, address, and write
data for SDRAM and the latch timing of read data from
SDRAM. Setting this bit makes the hold time for command,
address, write and read data extended. This mode is suitable
for SDRAM with low-frequency clock.
0: Command, address, and write data for SDRAM is output at
the rising edge of CKIO. Read data from SDRAM is
latched at the rising edge of CKIO.
1: Command, address, and write data for SDRAM is output at
the falling edge of CKIO. Read data from SDRAM is
latched at the falling edge of CKIO.
Rev. 2.00, 09/03, page 175 of 690