HD6417705F133V Datasheet, PDF (148/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 4.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1)
LRU (Bits 5 to 0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Way to be Replaced
1
0
4.2.3 Cache Control Register 3 (CCR3)
The CCR3 register controls the cache size to be used. The cache size must be specified according
to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the
LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the
CCR3 register should be placed in un-cached address space. In addition, note that all cache entries
must be invalidated by setting the CF bit of the CCR1 to 1 before accessing the cache after the
CCR3 is modified.
Bit
31 to 24
Bit
Name
—
Initial
Value
0
23 to 16 CSIZE7 to H'01
CSIZE0
15 to 0 —
0
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Cache Size
Specify the cache size as shown below.
0000 0001: 16-kbyte cache
0000 0010: 32-kbyte cache
Settings other than above are prohibited.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00, 09/03, page 100 of 690