HD6417705F133V Datasheet, PDF (443/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit
Name Value R/W Description
0
DR
0
R/(W)^* Receive Data Ready
Indicates that there are fewer than the receive trigger
set number of data bytes in SCFRDR and no further
data will arrive in asynchronous mode.
0: Reception is in progress or has ended successfully
and there is no receive data left in SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When all the receive data in SCFRDR has been
read, and 0 is written to DR after reading DR = 1
1: No further receive data has arrived
[Setting condition]
When SCFRDR contains fewer than the receive trigger
set number of receive data bytes and no further data
will arrive.^{* 1}
Note: 1. The DR bit is set 15 etu after the last data is
received at a sampling rate of 1/16 regardless
of the setting of the sampling control bits in
SCSMR.
etu: Elementary time unit (time for transfer of
one bit)
Note: * Only 0 can be written for clearing the flags.
16.3.9 Bit Rate Register (SCBRR)
SCBRR is an 8-bit readable/writable register that sets the serial transfer bit rate in accordance with
the baud rate generator operating clock selected by bits CKS1 and CKS0 in SCSMR.
Bit
Initial
Bit
Name Value R/W Description
7 to 0
SCBR7 H'FF
to
SCBR0
R/W Bit Rate Setting
The SCBRR setting is found from the following equation.
Rev. 2.00, 09/03, page 395 of 690