HD6417705F133V Datasheet, PDF (475/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 16.4 SCIF Interrupt Sources
Interrupt Source Description
DMAC Activation
ERI
Interrupt initiated by receive error flag (ER) or break Not possible
flag (BRK)
RXI
Interrupt initiated by receive FIFO data full flag (RDF) Possible^*1
or receive data ready (DR)
TXI
Interrupt initiated by transmit FIFO data
Possible^*2
empty flag (TDFE) or transmit data stop flag (TSF)
Notes: 1. The DMAC can be activated only by a receive-FIFO-data-full interrupt request.
2. The DMAC can be activated by a transmit-FIFO-data-empty (TDFE) or transmit-data-
stop (TSF) interrupt request. When the DMAC is activated by the TSF interrupt, it is
cleared by either of two cases listed below.
(1) The TSF flag is read by the CPU.
(2) The transmit FIFO is full.
See section 5, Exception Handling, for priorities and the relationship with non-SCIF interrupts.
Rev. 2.00, 09/03, page 427 of 690