HD6417705F133V Datasheet, PDF (719/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.11 SCIF Module Signal Timing
Table 25.13 SCIF Module Signal Timing
(Conditions: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to
1.6 V, AVCC = 3.0 to 3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-PLL2 =
AVSS = 0 V, Ta = –20 to 75°C)
Module Item
Symbol Min Max
Unit Figure
SCIF0,
SCIF2
Input clock
cycle
Clock
tScyc
synchronization
12
—
tpcyc
25.49
25.50
Asynchroniza-
tion
4
—
Input clock rise time
tSCKr
—
1.5
25.49
Input clock fall time
tSCKf
—
1.5
Input clock pulse width
tSCKW
0.4
0.6
tscyc
Transmission data delay time tTXD
(clock synchronization)
—
3 tpcyc^* + 50 ns
25.50
Receive data setup time
(clock synchronization)
tRXS
2 tpcyc^* —
Receive data hold time
(clock synchronization)
RTS delay time
(clock synchronization)
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
tRXH
tRTSD
tCTSS
tCTSH
2 tpcyc^* —
—
100
100 —
100 —
Note: * tpcyc indicates a peripheral clock (Pφ) cycle.
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 25.49 SCK Input Clock Timing
Rev. 2.00, 09/03, page 671 of 690