HD6417705F133V Datasheet, PDF (261/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 7.16 shows a timing chart in burst read. In burst read, an ACTV command is output in the
Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA command is
issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock
(CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto-
precharge induced by the READ command in the SDRAM. In the Tap cycle, a new command
will not be issued to the same bank. However, access to another CS space or another bank in the
same SDRAM space is enabled. The number of Tap cycles is specified by the TRP[1:0] bits of
the CS3WCR register.
CKIO
A25 to A0
A12/A11^*1
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Tw
Td1
Td2
Td3
Td4
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.16 Synchronous DRAM Burst Read Wait Specification Timing
(Auto Precharge)
Rev. 2.00, 09/03, page 213 of 690