HD6417705F133V Datasheet, PDF (461/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

In serial reception, the SCIF operates as described below.
1. The SCIF monitors the communication line, and if 0 of a start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
a. Stop bit check: the SCIF checks whether the stop bit is 1. If there are two stop bits, only the
first is checked.
b. The SCIF checks whether receive data can be transferred from the receive shift register
(SCRSR) to SCFRDR.
c. Break check: the SCIF checks that the BRK flag is 0, indicating that the break state is not
set.
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: Reception continues when a receive error (a framing error or parity error) occurs.
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
interrupt (RXI) request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
(ERI) request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt (BRI) request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive-data-ready
interrupt (DRI) request is generated.
The vectors of receive-FIFO-data-full and receive-data-ready interrupts are the same. The
vectors of receive-error and break reception interrupts are the same.
Rev. 2.00, 09/03, page 413 of 690