HD6417705F133V Datasheet, PDF (595/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.7 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data
specified by BDRB.
Bit
Bit
Name
Initial
Value R/W Description
31 to 0 BDMB31 to 0
BDMB0
R/W Break Data Mask B
Specifies bits masked in the break data of channel B
specified by BDRB (BDB31 to BDB0).
0: Break data BDBn of channel B is included in the
break condition
1: Break data BDBn of channel B is masked and is not
included in the break condition
Note: n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDRB as the break mask data in BDMRB.
22.2.8 Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of
channel B.
Bit
15 to 8
Bit
Name

Initial
Value
0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 547 of 690