HD6417705F133V Datasheet, PDF (175/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.2 Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Abbreviation I/O
Description
Nonmaskable interrupt input pin NMI
Input
Input of interrupt request signal, not
maskable by the interrupt mask bits
in SR
Interrupt input pins
IRQ5 to IRQ0, Input Input of interrupt request signals
to IRL3 IRL0
Port interrupt input pins
PINT15 to
PINT0
Input Input of port interrupt signals
Note: IRL3 to IRL0 are multiplexed with IRQ3 to IRQ0; they cannot be used together with IRQ3 to
IRQ0 at the same time.
6.3 Register Descriptions
The INTC has the following registers. For details on register addresses and register states during
each processing, refer to section 24, List of Registers.
• Interrupt control register 0 (ICR0)
• Interrupt control register 1 (ICR1)
• Interrupt control register 2 (ICR2)
• PINT interrupt enable register (PINTER)
• Interrupt priority level setting register A (IPRA)
• Interrupt priority level setting register B (IPRB)
• Interrupt priority level setting register C (IPRC)
• Interrupt priority level setting register D (IPRD)
• Interrupt priority level setting register E (IPRE)
• Interrupt priority level setting register F (IPRF)
• Interrupt priority level setting register G (IPRG)
• Interrupt priority level setting register H (IPRH)
• Interrupt request register 0 (IRR0)
• Interrupt request register 1 (IRR1)
• Interrupt request register 2 (IRR2)
Rev. 2.00, 09/03, page 127 of 690