HD6417705F133V Datasheet, PDF (602/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The eight BRDR registers have
a queue structure and a stored register is shifted at every branch.
Bit
31
30 to
28
27 to 0
Bit
Name
DVF
Initial
Value
0

0
BDA27 to Undefined
BDA0
R/W Description
R
BRDR Valid Flag
Indicates whether a branch destination address is
stored. When a branch destination address is
fetched, this flag is set to 1. This flag is cleared to 0
by reading BRDR.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
R
Reserved
These bits are always read as 0.
R
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
22.2.13 Break ASID Register A (BASRA)
BASRA is an 8-bit readable/writable register that specifies ASID which becomes the break
condition for channel A. BASRA is in CCN.
Bit
7 to 0
Bit
Name
BASA7
to
BASA0
Initial
Value

R/W Description
R/W Break ASID A
Store ASID (bits 7 to 0) which is the break condition
for channel A.
Rev. 2.00, 09/03, page 554 of 690