HD6417705F133V Datasheet, PDF (83/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

2.3.4 Control Registers
The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
Status Register (SR): The status register (SR) indicates the system status as shown below. The
SR register can be accessed only in privileged mode.
Initial
Bit Bit Name Value R/W
31

0
R
30
MD
1
R/W
29
RB
1
R/W
28
BL
1
R/W
27 to 10 
0
R
Description
Reserved
This bit is always read as 0. The write value should always be
0.
Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling state.
Register Bank
The general registers R0 to R7 are banked registers. The RB
bit selects a bank used in the privileged mode.
0: Selects bank 0 registers. In this case, R0_BANK0 to
R7_BANK0 and R8 to R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the LDC or
STR instruction.
1: Selects bank 1 registers. In this case, R0_BANK1 to
R7_BANK1 and R8 to R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the LDC or
STR instruction.
The RB bit is set to 1 in reset or exception handling state.
Block
Specifies whether an exception, interrupt, or user break is
enabled or not.
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling state.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 35 of 690