HD6417705F133V Datasheet, PDF (227/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

7.4.6 Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit counter that counts up using the clock selected by bits CKS2 to CKS0 in
RTCSR.
This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits
of the data must be H'A55A, otherwise writing cannot be performed. When reading, the upper 16
bits are read as H'0000.
When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after
counting up to 255.
Bit
Bit Name
31 to 8 
7 to 0 
Initial
Value R/W
0
R
0
R/W
Description
Reserved
8-Bit Counter
7.4.7 Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
This register only accepts 32-bit writing to prevent incorrect writing. In this case, the upper 16 bits
of the data must be H'A55A, otherwise writing cannot be performed. When reading, the upper 16
bits are read as H'0000.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
When the CMIE bit in RTCSR is 1, an interrupt request is issued by this matching signal. This
request signal is output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects
the interrupt and does not affect the refresh request. Accordingly, the refresh requests and interval
timer interrupts can be used together. For example, the number of refresh requests can be counted
by using interrupts while the refresh is performed.
Rev. 2.00, 09/03, page 179 of 690