HD6417705F133V Datasheet, PDF (618/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
15 to 13
12
11 to 8
Bit
Name
TI7 to TI5
TI4
TI3 to TI0
7 to 2 
1

0

Initial
Value R/W
1
R
0
R
1
R
1
R
0
R
1
R
Description
Test Instruction 7 to 0
The UDI instruction is transferred to SDIR by a
serial input from TDI.
For commands, see table 23.2.
Reserved
These bits are always read as 1.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.
Table 23.2 UDI Commands
Bits 15 to 8
TI7 TI6 TI5 TI4 TI3 TI2 TI1 TI0 Description
0
0
0
0
—
—
—
—
JTAG EXTEST
0
0
1
0
—
—
—
—
JTAG CLAMP
0
0
1
1
—
—
—
—
JTAG HIGHZ
0
1
0
0
—
—
—
—
JTAG SAMPLE/PRELOAD
0
1
1
0
—
—
—
—
UDI reset negate
0
1
1
1
—
—
—
—
UDI reset assert
1
0
1
—
—
—
—
—
UDI interrupt
1
1
1
0
—
—
—
—
JTAG IDCODE (Initial value)
1
1
1
1
—
—
—
—
JTAG BYPASS
Other than the above
Reserved
23.3.3 Boundary Scan Register (SDBSR)
SDBSR is a 385-bit shift register, located on the PAD, for controlling the input/output pins of this
LSI. The initial value is undefined. SDBSR cannot be accessed by the CPU.
Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan
test which supports the JTAG standard can be carried out. Table 23.3 shows the correspondence
between this LSI’s pins and boundary scan register bits.
Rev. 2.00, 09/03, page 570 of 690