HD6417705F133V Datasheet, PDF (30/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.6.2 Forcible Stall by Application ........................................................................... 465
18.6.3 Automatic Stall by USB Function Module ....................................................... 467
18.7 DMA Transfer ............................................................................................................. 468
18.7.1 Overview ........................................................................................................ 468
18.7.2 DMA Transfer for Endpoint 1.......................................................................... 468
18.7.3 DMA Transfer for Endpoint 2.......................................................................... 469
18.8 Example of USB External Circuitry.............................................................................. 470
18.9 Usage Notes................................................................................................................. 473
18.9.1 Receiving Setup Data ...................................................................................... 473
18.9.2 Clearing the FIFO ........................................................................................... 473
18.9.3 Overreading and Overwriting the Data Registers.............................................. 473
18.9.4 Assigning Interrupt Sources to EP0.................................................................. 474
18.9.5 Clearing the FIFO when DMA Transfer Is Enabled.......................................... 474
18.9.6 Notes on TR Interrupt...................................................................................... 474
Section 19 Pin Function Controller.................................................................475
19.1 Overview..................................................................................................................... 475
19.2 Register Descriptions................................................................................................... 479
19.2.1 Port A Control Register (PACR)...................................................................... 480
19.2.2 Port B Control Register (PBCR) ...................................................................... 481
19.2.3 Port C Control Register (PCCR) ...................................................................... 483
19.2.4 Port D Control Register (PDCR)...................................................................... 485
19.2.5 Port E Control Register (PECR)....................................................................... 487
19.2.6 Port E Control Register 2 (PECR2).................................................................. 488
19.2.7 Port F Control Register (PFCR) ....................................................................... 489
19.2.8 Port F Control Register 2 (PFCR2) .................................................................. 490
19.2.9 Port G Control Register (PGCR)...................................................................... 491
19.2.10 Port H Control Register (PHCR)...................................................................... 493
19.2.11 Port J Control Register (PJCR) ........................................................................ 494
19.2.12 Port K Control Register (PKCR)...................................................................... 496
19.2.13 Port L Control Register (PLCR)....................................................................... 498
19.2.14 Port M Control Register (PMCR)..................................................................... 499
19.2.15 Port N Control Register (PNCR)...................................................................... 500
19.2.16 Port N Control Register 2 (PNCR2) ................................................................. 502
19.2.17 Port SC Control Register (SCPCR) .................................................................. 503
Section 20 I/O Ports .......................................................................................507
20.1 Port A.......................................................................................................................... 507
20.1.1 Register Description ........................................................................................ 507
20.1.2 Port A Data Register (PADR) .......................................................................... 508
20.2 Port B.......................................................................................................................... 508
20.2.1 Register Description ........................................................................................ 509
20.2.2 Port B Data Register (PBDR)........................................................................... 509
Rev. 2.00, 09/03, page xxviii of xlvi