HD6417705F133V Datasheet, PDF (195/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.5.2 Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT or INTEVT2.
The code in INTEVT or INTEVT2 can be used as an offset for branching to the specific
handler.
2. Clear the interrupt source in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. Figure 6.3 shows a sample interrupt operation
flowchart.
6.6 Usage Note
The interrupt accept timing in this LSI is not acknowledged externally. Thus, keep the following
note in mind when designing the system.
• Level interrupt
The level interrupt request should be held until the CPU accepts it. The level interrupt request
needs to be cleared (released) within the specific interrupt handler. If the level interrupt request
is not held, the operation may branch to the interrupt handling routine when the value in
INTEVT/2 becomes H'000.
When the standby state is cancelled, if the level interrupt request is not held, the operation will
go back to the standby state again in the middle of WDT counting. When canceling the
standby state again in such a condition by asserting the level interrupt request, the settling time
for the PLL or crystal oscillator is not secured enough and the operation may not recover from
the standby state correctly.
• Interrupt flag update
When an interrupt is acceptable and the generation of an interrupt request is enabled, updating
or clearing the interrupt flag may branch the operation to the interrupt handling routine when
the value in INTEVT2 becomes H'000.
Rev. 2.00, 09/03, page 147 of 690