HD6417705F133V Datasheet, PDF (450/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

16.4 Operation
16.4.1 Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character, and in clock synchronous mode, in which synchronization is
achieved with clock pulses.
64-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
16.4.2 Asynchronous Mode
The transfer format is selected using the serial mode register (SCSMR), as shown in table 16.2.
The SCIF clock source is determined by the CKE1 and CKE0 bits in the serial control register
(SCSCR).
• Data length: Choice of seven or eight bits
• Choice of parity addition and addition of one or two stop bits (the combination of these
parameters determines the transfer format and character length)
• Detection of framing errors, parity errors, overrun errors, receive-FIFO-data-full state, receive-
data-ready state, and breaks, during reception
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Choice of internal or external clock as the SCIF clock source
 When internal clock is selected: the SCIF operates on the baud rate generator clock.
 When external clock is selected: A clock must be input according to the sampling rate. For
example, when the sampling rate is 1/16, a clock with a frequency of 8 times the bit rate
must be input (the on-chip baud rate generator is not used.)
Rev. 2.00, 09/03, page 402 of 690