HD6417705F133V Datasheet, PDF (500/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit Bit Name Initial Value R/W Description
0
EP1DMAE 0
R/W Endpoint 1 DMA Transfer Enable
When this bit is set, DMA transfer is enabled from the
endpoint 1 receive FIFO buffer to memory. If there is at
least one byte of receive data in the FIFO buffer, a
transfer request is asserted for the DMAC. In DMA
transfer, when all the received data is read, EP1 is read
automatically and the completion trigger operates.
EP1-related interrupt requests to the CPU are not
automatically masked.
• Operating procedure:
1. Write of 1 to the EP1 DMAE bit in DMAR
2. Transfer count setting in the DMAC
3. DMAC activation
4. DMA transfer
5. DMA transfer end interrupt generated
Refer to section 18.7.2, DMA Transfer for Endpoint 1.
Rev. 2.00, 09/03, page 452 of 690