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HD6417705F133V Datasheet, PDF (103/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series | |||
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Instruction
Instruction Code Operation
Privileged
Mode Cycles T Bit
EXTS.B Rm,Rn
0110nnnnmmmm1110 A byte in Rm is sign-extended â â
Rn
1
â
EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign-extended â
â Rn
1
â
EXTU.B Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero-extended â â
Rn
1
â
EXTU.W Rm,Rn
MAC.L
@Rm+,
@Rn+
MAC.W
@Rm+,
@Rn+
MUL.L Rm,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
0110nnnnmmmm1101 A word in Rm is zero-extended â
â Rn
0000nnnnmmmm1111
Signed operation of (Rn) Ã (Rm) â
+ MAC â MAC,Rn + 4 â Rn,
Rm + 4 â Rm,
32 Ã 32 + 64 â 64 bits
0100nnnnmmmm1111
Signed operation of (Rn) Ã (Rm) â
+ MAC â MAC,Rn + 2 â Rn,
Rm + 2 â Rm,
16 Ã 16 + 64 â 64 bits
0000nnnnmmmm0111 Rn à Rm â MACL,
â
32 Ã 32 â 32 bits
0010nnnnmmmm1111 Signed operation of Rn à Rm â â
MACL,
16 Ã 16 â 32 bits
0010nnnnmmmm1110 Unsigned operation of Rn à Rm â
â MACL,
16 Ã 16 â 32 bits
1
â
2 (to 5)* â
2 (to 5)* â
2 (to 5)* â
1(to 3)* â
1(to 3)* â
NEG
Rm,Rn
0110nnnnmmmm1011 0âRmâRn
â
1
â
NEGC
Rm,Rn
0110nnnnmmmm1010 0âRmâTâRn, BorrowâT
â
1
Borrow
SUB
Rm,Rn
0011nnnnmmmm1000 RnâRmâRn
â
1
â
SUBC
Rm,Rn
0011nnnnmmmm1010 RnâRmâTâRn, Borrow âT
â
1
Borrow
SUBV
Note:
Rm,Rn
0011nnnnmmmm1011 RnâRmâRn, UnderflowâT
â
1
Underflow
* The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Rev. 2.00, 09/03, page 55 of 690
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