HD6417705F133V Datasheet, PDF (441/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W
Description
4 BRK 0
R/(W)^*
Break Detect
Indicates that a receive data break signal has been
detected in asynchronous mode.
0: A break signal has not been received
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to BRK after reading BRK = 1
1: A break signal has been received^*1
[Setting condition]
When data with a framing error is received, followed by the
space 0 level (low level) for at least one frame length
Note: 1.
When a break is detected, the receive data
(H'00) following detection is not transferred to
SCFRDR. When the break ends and the receive
signal returns to mark 1, receive data transfer is
resumed.
3 FER 0
R
Framing Error
Indicates a framing error in the data read from SCFRDR in
asynchronous mode.
0: There is no framing error in the receive data read from
SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When there is no framing error in SCFRDR read data
1: There is a framing error in the receive data read from
SCFRDR
[Setting condition]
When there is a framing error in SCFRDR read data
Rev. 2.00, 09/03, page 393 of 690