HD6417705F133V Datasheet, PDF (501/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.3.19 Endpoint Stall Register (EPSTL)
The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set
to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 is
cleared automatically on reception of 8-byte command data for which decoding is performed by
the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to
1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 18.6, Stall
Operations.
Bit Bit Name
7 to 4 
3
EP3STL
2
EP2STL
1
EP1STL
0
EP0STL
Initial Value R/W
0
R
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
EP3 Stall
When this bit is set to 1, endpoint 3 is placed in the
stall state.
EP2 Stall
When this bit is set to 1, endpoint 2 is placed in the
stall state.
EP1 Stall
When this bit is set to 1, endpoint 1 is placed in the
stall state.
EP0 Stall
When this bit is set to 1, endpoint 0 is placed in the
stall state.
18.3.20 Transceiver Control Register (XVERCR)
The Transceiver Control Register sets either the internal transceiver or external transceiver for use.
Bit Bit Name
7 to 1 
Initial Value R/W
0
R
0
XVEROFF 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transceiver Control
1: The internal transceiver function is stopped and a
digital signal for the external transceiver is output
from the port.
0: The internal transceiver is operated.
Rev. 2.00, 09/03, page 453 of 690