HD6417705F133V Datasheet, PDF (630/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

3. EXTEST:
This instruction is provided to test external circuitry when this LSI is mounted on a printed
circuit board. When this instruction is executed, output pins are used to output test data
(previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the
printed circuit board, and input pins are used to latch test results into the boundary scan
register from the printed circuit board. If testing is carried out by using the EXTEST
instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out.
Data loaded into the output pin boundary scan register in the Capture-DR state is not used for
external circuit testing (it is replaced by a shift operation).
The upper four bits of the instruction code are 0000.
4. IDCODE:
A command can be set in SDIR by the UDI pins to place the UDI pins in the IDCODE mode
stipulated by JTAG. When the UDI is initialized (TRST is asserted or TAP is in the Test-
Logic-Reset state), the IDCODE mode is entered.
5. CLAMP, HIGHZ:
A command can be set in SDIR by the UDI pins to place the UDI pins in the CLAMP or
HIGHZ mode stipulated by JTAG.
23.5.2 Points for Attention
1. Boundary scan mode does not cover clock-related signals (EXTAL, EXTAL2, XTAL,
XTAL2, EXTAL_USB, XTAL_USB, and CKIO).
2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM, and CA).
3. Boundary scan mode does not cover UDI-related signals (TCK, TDI, TDO, TMS, and TRST).
4. Fix the RESETP pin low during boundary scan.
5. Fix the CA pin high during boundary scan.
6. Fix the ASEMD0 pin high during boundary scan.
7. The CKIO cock should operate during boundary scan. The MD[2:0] pin should be set to the
clock mode used during normal operation, and EXTAL and CKIO should be set within the
frequency range specified in the Clock Pulse Generator (CPG) section.
As during normal operation, the boundary scan test should be performed after allowing
sufficient settling time for the crystal oscillator, PLL1, and PLL2.
Rev. 2.00, 09/03, page 582 of 690