HD6417705F133V Datasheet, PDF (151/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

4.3.5 Write-Back Buffer
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 4.3 shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address written to external memory
Longword 0 to 3: One line of cache data to be written to external
memory
Figure 4.3 Write-Back Buffer Configuration
4.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
Rev. 2.00, 09/03, page 103 of 690