HD6417705F133V Datasheet, PDF (338/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

WTCNT write
15
87
0
H'5A
Write data
WTCSR write
15
H'A5
87
0
Write data
Figure 10.2 Writing to WTCNT and WTCSR
10.3 Operation
10.3.1 Canceling Software Standbys
The WDT is used to cancel software standby mode with an interrupt such as an NMI. The
procedure when using an NMI interrupt is described below. (The WDT does not run when resets
are used for canceling, so keep the RESETP or RESETM pin low until the clock stabilizes.)
1. Before transitioning to software standby mode, always clear the TME bit in WTCSR to 0.
When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when
the count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. Move to software standby mode by executing a SLEEP instruction, after that clock stops.
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set.
6. Since the WDT continues counting from H'00, clear the STBY bit in the STBCR register to 0
in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1,
the LSI again enters the software standby mode when the WDT has counted up to H'80. This
software standby mode can be canceled by power-on resets.
Rev. 2.00, 09/03, page 290 of 690