HD6417705F133V Datasheet, PDF (439/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W
Description
8 TSF 0
R/(W)^* Transmit Data Stop
Indicates that the number of transmit data matches the
value of SCTDSR.
0: Number of transmit data does not match the value of
SCTDSR
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to TSF after reading TSF = 1
1: Number of transmit data matches the value of SCTDSR
7 ER
0
R/(W)^* Receive Error
Indicates that a framing error or parity error occurred during
reception in asynchronous mode.^*1
0: No framing error or parity error occurred during reception
[Clearing conditions]
• Power-on reset or manual reset
• When 0 is written to ER after reading ER = 1
1: A framing error or parity error occurred during reception
[Setting conditions]
• When the SCIF checks whether the stop bit at the end
of the receive data is 1 when reception ends, and the
stop bit is 0^*2
• When, in reception, the number of 1-bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SCSMR
Notes: 1. The ER flag is not affected and retains its
previous state when the RE bit in SCSCR is
cleared to 0. When a receive error occurs, the
receive data is still transferred to SCFRDR, and
reception continues.
The FER and PER bits in SCSSR can be used
to determine whether there is a receive error in
the data read from SCFRDR.
2. When the stop length is two bits, only the first
stop bit is checked for a value of 1; the second
stop bit is not checked.
Rev. 2.00, 09/03, page 391 of 690