HD6417705F133V Datasheet, PDF (14/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Item
6.1 Features
Figure 6.1 Block Diagram
of INTC
Page
126
Revisions (See Manual for Details)
CMT deleted
NMI
IRQ5−IRQ0
PINT15−PINT0
DMAC
SCIF
ADC
USB
Input/output
6
control
16
(Interrupt request)
TMU
6.4.6 Interrupt Exception 140
Handling and Priority
Table 6.4 Interrupt
Exception Handling Sources
and Priority (IRQ Mode)
7.4.2 CSn Space Bus
160
Control Register (CSnBCR)
(n = 0, 2, 3, 4, 5A, 5B, 6A,
6B)
161
7.4.5 Refresh Timer
177
Control/Status Register
(RTCSR)
Legend:
DMAC : Direct memory access controller
SCIF : Serial communication interface (with FIFO)
ADC : A/D converter
USB : USB interface
TMU : Timer pulse unit
TPU : 16-bit timer pulse unit
IPR (bit numbers) amended for interrupt source TMU2
IPRA (7 to 4)
Bits 14 to 12 description added
Note: SDRAM can be specified only in area 2 and area 3. If
SDRAM is connected to only one area, SDRAM should be
specified for area 3. In this case area 2 should be specified
as normal space.
Note 5 added
Note: 5. The SDRAM bank active mode can only be used
for the CS3 space. (Refer to the explanation of the BACTV
bit in the SDRAM control register.)
Bits 31 to 18 description amended
Bit
Initial
Bit
Name Value R/W Description
31 to 8 
0
R
Reserved
7.4.6 Refresh Timer
Counter (RTCNT)
179 Bits 31 to 18 description amended
Bit
Initial
Bit
Name Value R/W Description
31 to 8 
0
R
Reserved
Rev. 2.00, 09/03, page xii of xlvi