HD6417705F133V Datasheet, PDF (209/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Initial
Bit Name Value R/W Description
8 to 0 
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Notes: 1. When the CS5B space is specified as address/data multiplex I/O (MPX), specify the
bus size to 16 bits.
2. The data bus size of the CS0 space is specified by an external input pin. The value of
BSZ[1:0] bits in CS0BCR are invalid.
3. When both the CS2 and CS3 spaces are specified as the SDRAM space, specify the
same bus size for the CS2 and CS3 spaces.
4. When the CS2 or CS3 space is specified as the SDRAM space, specify the bus width to
16 bits or 32 bits.
5. The SDRAM bank active mode can only be used for the CS3 space. (Refer to the
explanation of the BACTV bit in the SDRAM control register.)
6. The initial values of the bus size assignment for areas 5B, 6A, and 6B after power-on
reset is specified to prohibited setting. Therefore, specify the 8- or 16-bit size before
accessing these areas.
7. When port A or B is used, specify the bus size of all areas to 8 bits or 16 bits.
When the memory type is specified to an area other than the areas that can be specified, the
operation of this LSI is not guaranteed.
7.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
CSnWCR is a 32-bit readable/writable register that specifies various wait cycles for memory
accesses. The bit configuration of this register varies as shown below according to the memory
type (TYPE 2, TYPE 1, or TYPE 0) specified by the CSn space bus control register (CSnBCR).
Specify the CSnWCR register before accessing the target area. Specify CSnBCR register first,
then specify the CSnWCR register.
Rev. 2.00, 09/03, page 161 of 690