HD6417705F133V Datasheet, PDF (285/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
BREQ
BACK
A25 to A0
Data
CSn
Other bus
control signals
Figure 7.34 Bus Arbitration
In an original slave device designed by the user, multiple bus accesses are generated continuously
to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh
correctly, the slave device must be designed to release the bus mastership within the refresh
interval time.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
7.13 Others
Reset: The bus state controller (BSC) can be initialized completely only at power-on reset. At
power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle
state. All control registers are initialized.
In standby, sleep, and manual reset, control registers of the bus state controller are not initialized.
At manual reset, the current bus cycle being executed is completed and then the access wait state
is entered. Since the RTCNT continues counting up during manual reset signal assertion, a refresh
request occurs to initiate the refresh cycle.
Note that arbitration requests using BREQ are not accepted during manual reset signal assertion.
On-Chip Peripheral Module Access: To access an on-chip module register, two or more
peripheral module clock (Pφ) cycles are required. Care must be taken in system design.
Rev. 2.00, 09/03, page 237 of 690