HD6417705F133V Datasheet, PDF (460/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Error handling
ER = 1?
Yes
Receive error handling
BRK = 1?
Yes
Break handling
No
[1]
No
[2]
[1] Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR can be ascertained from the FER
and PER bits in SCSSR.
[2] When a break signal is received, receive data
is not transferred to SCFRDR while the BRK
flag is set. However, note that the last data in
SCFRDR is H'00 and the break data in which
a framing error occurred is stored.
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, and BRK flags
in SCSSR to 0
End
Figure 16.8 Sample Serial Reception Flowchart (2)
Rev. 2.00, 09/03, page 412 of 690