HD6417705F133V Datasheet, PDF (351/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

11.8 Timing of STATUS Pin Changes
The timing of the STATUS0 and STATUS1 pin changes is shown in figures 11.2 to 11.9.
In Case of A Reset:
a. Power-on reset
CKIO
RESETP
PLL settling
time
STATUS
Normal^*2
Reset^*1
0 to 5 Bcyc^*3
0 to 30 Bcyc^*3
Notes: 1. Reset: HH (STATUS1 high, STATUS0 high)
2. Normal: LL (STATUS1 low, STATUS0 low)
3. Bcyc: Bus clock cycle
Normal^*2
Figure 11.2 Power-On Reset STATUS Output
b. Manual reset
CKIO
RESETM
STATUS
Normal^*3
Reset^*2
Normal^*3
0 Bcyc or more^*1,4
0 to 30 Bcyc^*4
Notes: 1. During manual reset, STATUS becomes HH (reset) and the internal
reset begins after waiting for the executing bus cycle to end.
2. Reset: HH (STATUS1 high, STATUS0 high)
3. Normal: LL (STATUS1 low, STATUS0 low)
4. Bcyc: Bus clock cycle
Figure 11.3 Manual Reset STATUS Output
Rev. 2.00, 09/03, page 303 of 690