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HD6417705F133V Datasheet, PDF (647/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
Register Bit 31/ Bit 30/ Bit 29/ Bit 28/ Bit 27/ Bit 26/ Bit 25/ Bit 24/
Abbreviation 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 Module
CS6BBCR 

IWW1 IWW0 
IWRWD1 IWRWD0 
BSC
IWRWS1 IWRWS0 
IWRRD1 IWRRD0 
IWRRS1 IWRRS0

TYPE2 TYPE1 TYPE0 
BSZ1
BSZ0 








CS0W CR








(except burst 







ROM)



SW1 SW0
WR3
WR2 WR1
WR0 WM




HW1 HW0
CS0W CR








(burst ROM) 





BW1 BW0





W3
W2
W1
W0
WM






CS2 WCR 




(except





SDRAM)







WR3


WR2


WR1
WR0 WM






CS2 WCR 







(SDRAM)















A2CL1
A2CL0 






CS3 WCR 




(except





SDRAM)







WR3


WR2


WR1
WR0 WM






CS3 WCR 







(SDRAM)









TRP1 TRP0 
TRCD1 TRCD0 
A3CL1
A3CL0 


TRWL1 TRWL0 TRC1 TRC0
CS4 WCR 







(except burst 




ROM)
WW2 WW1 WW0



SW1 SW0
WR3
WR2 WR1
WR0 WM




HW1 HW0
Rev. 2.00, 09/03, page 599 of 690