HD6417705F133V Datasheet, PDF (29/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

17.3 Register Description..................................................................................................... 432
17.3.1 IrDA Mode Register (SCSMR_Ir).................................................................... 432
17.4 Operation..................................................................................................................... 434
17.4.1 Overview......................................................................................................... 434
17.4.2 Transmitting.................................................................................................... 434
17.4.3 Receiving ........................................................................................................ 435
17.4.4 Data Format Specification ............................................................................... 435
Section 18 USB Function Module.................................................................. 437
18.1 Features ....................................................................................................................... 437
18.2 Input/Output Pins......................................................................................................... 439
18.3 Register Descriptions ................................................................................................... 440
18.3.1 Interrupt Flag Register 0 (IFR0)....................................................................... 441
18.3.2 Interrupt Flag Register 1 (IFR1)....................................................................... 442
18.3.3 Interrupt Select Register 0 (ISR0) .................................................................... 443
18.3.4 Interrupt Select Register 1 (ISR1) .................................................................... 443
18.3.5 Interrupt Enable Register 0 (IER0)................................................................... 444
18.3.6 Interrupt Enable Register 1 (IER1)................................................................... 444
18.3.7 EP0i Data Register (EPDR0i) .......................................................................... 445
18.3.8 EP0o Data Register (EPDR0o)......................................................................... 445
18.3.9 EP0s Data Register (EPDR0s) ......................................................................... 445
18.3.10 EP1 Data Register (EPDR1) ............................................................................ 446
18.3.11 EP2 Data Register (EPDR2) ............................................................................ 446
18.3.12 EP3 Data Register (EPDR3) ............................................................................ 446
18.3.13 EP0o Receive Data Size Register (EPSZ0o)..................................................... 447
18.3.14 EP1 Receive Data Size Register (EPSZ1)......................................................... 447
18.3.15 Trigger Register (TRG) ................................................................................... 448
18.3.16 Data Status Register (DASTS) ......................................................................... 449
18.3.17 FIFO Clear Register (FCLR)............................................................................ 449
18.3.18 DMA Transfer Setting Register (DMAR)......................................................... 450
18.3.19 Endpoint Stall Register (EPSTL) ..................................................................... 453
18.3.20 Transceiver Control Register (XVERCR)......................................................... 453
18.4 Operation..................................................................................................................... 454
18.4.1 Cable Connection ............................................................................................ 454
18.4.2 Cable Disconnection........................................................................................ 455
18.4.3 Control Transfer .............................................................................................. 455
18.4.4 EP1 Bulk-Out Transfer (Dual FIFOs)............................................................... 461
18.4.5 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................. 462
18.4.6 EP3 Interrupt-In Transfer................................................................................. 463
18.5 Processing of USB Standard Commands and Class/Vendor Commands ........................ 464
18.5.1 Processing of Commands Transmitted by Control Transfer .............................. 464
18.6 Stall Operations ........................................................................................................... 465
18.6.1 Overview......................................................................................................... 465
Rev. 2.00, 09/03, page xxvii of xlvi