HD6417705F133V Datasheet, PDF (679/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.1 Clock Timing
Table 25.5 Clock Timing
(Condition: VCCQ = VCC-RTC = VCC-USB = 3.0 to 3.6 V, VCC = VCC-PLL1 = VCC-PLL2 = 1.4 to 1.6 V,
AVCC = 3.0 to 3.6 V, VSSQ = VSS = VSS-RTC = VSS-USB = VSS-PLL1 = VSS-PLL2 = AVSS =
0 V, Ta = –20 to 75°C, Maximum External Bus Operating Frequency: 66.67 MHz)
Item
Symbol Min
Max Unit Figure
EXTAL clock input frequency
fEX
10
66.67 MHz 25.2
EXTAL clock input cycle time
tEXcyc
15
100 ns
EXTAL clock input low pulse width
tEXL
1.5
— ns
EXTAL clock input high pulse width
tEXH
1.5
— ns
EXTAL clock input rise time
EXTAL clock input fall time
tEXr
—
6
ns
tEXf
—
6
ns
CKIO clock input frequency
fCKI
20
66.67 MHz 25.3
CKIO clock input cycle time
tCKICYC
15
50 ns
CKIO clock input low pulse width
tCKIL
3
— ns
CKIO clock input high pulse width
tCKIH
3
— ns
CKIO clock input rise time
tCKIR
—
4
ns
CKIO clock input fall time
tCKIF
—
4
ns
CKIO clock output frequency
CKIO clock output cycle time
tOP
20
66.67 MHz 25.4
tcyc
15
50 ns
CKIO clock output low pulse width
tCKOL
3
— ns
CKIO clock output high pulse width
tCKOH
3
— ns
CKIO clock output rise time
tCKOr
—
5
ns
CKIO clock output fall time
tCKOf
—
5
ns
Power-on oscillation settling time
RESETP setup time
RESETP assert time
RESETM assert time
tOSC1
10
tRESPS
20
tRESPW
20
tRESMW
20
— ms 25.5
— ns 25.5
— tcyc 25.5, 25.6
—
tcyc 25.6
Standby return oscillation settling time 1 tOSC2
Standby return oscillation settling time 2 tOSC3
10
— ms 25.6
10
— ms 25.7
Standby return oscillation settling time 3 tOSC4
11
— ms 25.8
Rev. 2.00, 09/03, page 631 of 690