HD6417705F133V Datasheet, PDF (317/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive
DMAC
2nd acceptance
Acceptance
start
CKIO
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive
DMAC
2nd acceptance
DMAC
3rd
acceptance
Acceptance
start
Acceptance
start
Figure 8.16 Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
Bus cycle
DREQ
DACK
DMAC
CPU
Last DMA transfer
DMAC
CPU
CPU
TEND
Figure 8.17 Example of DMA Transfer End Signal (in Cycle Steal Level Detection)
Rev. 2.00, 09/03, page 269 of 690