HD6417705F133V Datasheet, PDF (275/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

After self-refreshing has been set, the self-refresh state continues even if the chip standby state
is entered using the LSI standby function, and is maintained even after recovery from standby
mode other than through a power-on reset. In case of a power-on reset, the bus state
controller’s registers are initialized, and therefore the self-refresh state is cleared.
CKIO
CKE
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
Trc
Trc
Trc
Trc
CSn
RASU/L
CASU/L
RD/WR
DQMxx^*2
D31 to D0
BS
DACKn^*3
Hi-Z
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. xx is UU, UL, LU, or LL.
3. The waveform for DACKn is when active low is specified.
Figure 7.27 Self-Refresh Timing
3. Relationship between refresh requests and bus cycle
If a refresh request is generated during a bus cycle, refresh waits for the bus cycle to be
completed. If a refresh request is generated while the bus is released by the bus arbitration
function, refresh waits for the bus mastership to be obtained.
If a new refresh request is generated while refresh is waiting, the first refresh request is
canceled. To perform refresh correctly, the bus cycle and the bus-owned period must be shorter
than the refresh interval.
If a bus request is issued during self-refreshing, the bus is not released until the refresh is
completed.
Rev. 2.00, 09/03, page 227 of 690