HD6417705F133V Datasheet, PDF (85/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Vector Base Register (VBR): The global base register (GBR) can be accessed only in privileged
mode. If a transition from reset state to exception handling state occurs, this register is referenced
as a base address. For details, refer to section 5, Exception Handling. At reset, the VBR is
initialized as H'00000000.
Figure 2.6 shows the control register configuration.
Save status register (SSR)
31
0
SSR
Save program counter (SPC)
31
0
SPC
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
VBR
Status register (SR)
31
0 MD RB BL 0
0
0 M Q I3 I2 I1 I0 0 0 S T
Figure 2.6 Control Register Configuration
2.4 Data Formats
2.4.1 Register Data Format
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
Rev. 2.00, 09/03, page 37 of 690