HD6417705F133V Datasheet, PDF (318/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
Address
CSn
RD
Data
DACKn
TEND0
WAIT
T1 T2 Taw T1 T2
Note: TEND0 is asserted during the last transfer unit of
DMA transfer. When the transfer unit is divided into
several bus cycles and CS is negated between bus
cycles, TEND0 is also divided.
Figure 8.18 BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
8.5 Precautions
8.5.1 Precautions when Mixing Cycle-Steal Mode Channels and Burst Mode Channels
Transfer mode settings should not fulfill conditions (1) and (2) below at the same time.
(1) DMA transfer takes place using multiple channels, some of which operate in the burst mode
and some in the cycle-steal mode.
(2) A channel that uses the burst mode is set to dual address mode and DACK is output using the
write cycle.
Rev. 2.00, 09/03, page 270 of 690