HD6417705F133V Datasheet, PDF (406/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

15.3.8 Year Counter (RYRCNT)
The year counter (RYRCNT) is a 16-bit readable/writable register used for setting/counting in the
BCD-coded year section. The four digits of the western calendar year are counted. The count
operation is performed by a carry for each year of the month counter.
The range for year that can be set is 0000 to 9999 (decimal). Errant operation will result if any
other value is set. Carry out write processing after stopping the count operation with the START
bit in RCR2 or using a carry flag.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result
of 0. The year counter value 0000 is recognized as a leap year.
Bit
Bit Name
15 to 12 
Initial Value R/W

R/W
11 to 8 

R/W
7 to 4 

R/W
3 to 0 

R/W
Description
1000-unit of the year counter in the BCD-code.
The range that can be set is 0 to 9 (decimal).
100-unit of the year counter in the BCD-code.
The range that can be set is 0 to 9 (decimal).
10-unit of the year counter in the BCD-code.
The range that can be set is 0 to 9 (decimal).
1-unit of the year counter in the BCD-code.
The range that can be set is 0 to 9 (decimal).
15.3.9 Second Alarm Register (RSECAR)
The second alarm register (RSECAR) is an 8-bit readable/writable register, and an alarm register
corresponding to the second counter RSECCNT. When the ENB bit is set to 1, a comparison with
the RSECCNT value is performed. For alarm registers RSECAR, RMINAR, RHRAR, RWKAR,
RDAYAR, and RMONAR, a comparison with the corresponding counter value is performed for
those whose ENB bit is set to 1, and for RCR3, a comparison is performed when the YAEN bit is
set to 1. If all of those match, an RTC alarm interrupt is generated.
The range of second alarm that can be set is 00 to 59 (decimal). Errant operation will result if any
other value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset, and it is not initialized by manual
reset and standby mode. The remaining RSECAR fields are not initialized by a power-on reset or
manual reset, or in standby mode.
Rev. 2.00, 09/03, page 358 of 690