HD6417705F133V Datasheet, PDF (108/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Instruction
LDC.L @Rm+,
R6_BANK
LDC.L @Rm+,
R7_BANK
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
NOP
PREF @Rm
RTE
SETS
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC SSR, Rn
STC SPC,Rn
STC R0_BANK,Rn
STC R1_BANK,Rn
STC R2_BANK,Rn
STC R3_BANK,Rn
STC R4_BANK,Rn
STC R5_BANK,Rn
STC R6_BANK,Rn
STC R7_BANK,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
Instruction Code Operation
Privileged
Mode
Cycles T Bit
0100mmmm11100111 (Rm)→R6_BANK, Rm+4→Rm √
4
–
0100mmmm11110111 (Rm)→R7_BANK, Rm+4→Rm √
4
–
0100mmmm00001010 Rm→MACH
–
0100mmmm00011010 Rm→MACL
–
0100mmmm00101010 Rm→PR
–
0100mmmm00000110 (Rm)→MACH, Rm+4→Rm –
0100mmmm00010110 (Rm)→MACL, Rm+4→Rm
–
0100mmmm00100110 (Rm)→PR, Rm+4→Rm
–
0000000000111000 PTEH/PTEL→TLB
√
0000000000001001 No operation
–
0000mmmm10000011 (Rm) → cache
–
0000000000101011
Delayed branch, SSR → SR, √
SPC → PC
0000000001011000 1→S
–
0000000000011000 1→T
–
0000000000011011 Sleep
√
0000nnnn00000010 SR→Rn
√
0000nnnn00010010 GBR→Rn
–
0000nnnn00100010 VBR→Rn
√
0000nnnn00110010 SSR→Rn
√
0000nnnn01000010 SPC→Rn
√
0000nnnn10000010 R0_BANK→Rn
√
0000nnnn10010010 R1_BANK→Rn
√
0000nnnn10100010 R2_BANK→Rn
√
0000nnnn10110010 R3_BANK→Rn
√
0000nnnn11000010 R4_BANK→Rn
√
0000nnnn11010010 R5_BANK→Rn
√
0000nnnn11100010 R6_BANK→Rn
√
0000nnnn11110010 R7_BANK→Rn
√
0100nnnn00000011 Rn–4→Rn, SR→(Rn)
√
0100nnnn00010011 Rn–4→Rn, GBR→(Rn)
–
0100nnnn00100011 Rn–4→Rn, VBR→(Rn)
√
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
5
–
1
–
1
1
4^*1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
1
–
Rev. 2.00, 09/03, page 60 of 690