HD6417705F133V Datasheet, PDF (454/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 16.2 shows a sample SCIF initialization flowchart.
Initialization
Clear TE and RE bits
in SCSCR to 0
Set TFRST and RFRST bits
in SCFCR to 1
Set CKE1 and CKE0 bits
in SCSCR to B'00
(leaving TE and RE bits
[1]
cleared to 0)
Clear the C/A bit in SCSMR to 0, and
set the transmit/receive format
[2]
[1] Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE, and RE to 0.
[2] Set the transmit and receive format in SCSMR.
[3] Write a value corresponding to the bit rate into
SCBRR. (Not necessary if an external clock is
used.)
[4] Wait at least one bit interval, then set the TE bit
and RE bits in SCSCR to 1. Also set the RIE
and TIE bits.
Setting the TE and RE bits enables the TxD
and RxD pins to be used. When transmitting,
the TxD pin will go to the mark state; when
receiving, the RxD pin will go to the idle state.
Set value in SCBRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1−0 and
TTRG1−0 bits in SCFCR.
Clear TFRST and
RFRST bits to 0
Set TE and RE bits in SCSCR
to 1, and set RIE and TIE bits
[4]
End
Figure 16.2 Sample SCIF Initialization Flowchart
Rev. 2.00, 09/03, page 406 of 690