HD6417705F133V Datasheet, PDF (522/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

18.9.4 Assigning Interrupt Sources to EP0
The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must
be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.
18.9.5 Clearing the FIFO when DMA Transfer Is Enabled
The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is
enabled (EP1 DMAE in DMAR = 1). Cancel DMA transfer before clearing the register.
18.9.6 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP2, or EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 18.19, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note:
This module determines whether to return NAK if the FIFO of the target EP has no data
when receiving the IN token, but the TR interrupt flag is set only after a NAK handshake
is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag
is set again.
CPU
TR interrupt routine
Clear Writes
TRG.
TR flag transmit data PKTE
TR interrupt routine
Host
IN token
IN token
IN token
USB
Determines whether
to return NAK
NAK
Sets TR flag
Determines whether
to return NAK
Transmits data
NAK
Sets TR flag
(Sets the flag again)
ACK
Figure 18.19 TR Interrupt Flag Set Timing
Rev. 2.00, 09/03, page 474 of 690