HD6417705F133V Datasheet, PDF (319/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The CPG consists of oscillators, PLL circuits, and divider circuits.
9.1 Features
• Seven clock modes
Selection of seven clock modes depending on the frequency ranges and crystal oscillation or
external clock input.
• Three clocks generated independently
An internal clock for the CPU and cache (Iφ); a peripheral clock (Pφ) for the peripheral
modules; a bus clock (Bφ = CKIO) for the external bus interface.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the phase-locked
loop (PLL) circuit and divider circuit within the CPG. Frequencies are changed by software
using the frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped for sleep mode and software standby mode and specific modules can
be stopped using the module standby function.
A block diagram of the CPG is shown in figure 9.1.
CPGS312B_000020020100
Rev. 2.00, 09/03, page 271 of 690