HD6417705F133V Datasheet, PDF (365/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Bit
Bit Name Initial Value R/W Description
2
TPSC2
0
R/W Timer Prescaler
1
TPSC1
0
R/W Select the TCNT_2 count clock.
0
TPSC0
0
R/W 000: Count on Pφ/4
001: Count on Pφ/16
010: Count on Pφ/64
011: Count on Pφ/256
100: Setting prohibited
101: Count on TCLK pin input
110: Setting prohibited
111: Setting prohibited
Note: * Only 0 can be written for clearing the flags. If 1 is written to this bit, the prior value is
retained.
12.3.3 Timer Constant Registers (TCOR)
TCOR set the value to be set in TCNT when TCNT underflows.
TCOR are 32-bit readable/writable registers. Their initial value is H'FFFFFFFF.
12.3.4 Timer Counters (TCNT)
TCNT counts down upon input of a clock. The clock input is selected using the TPSC2 to TPSC0
bits in the timer control register (TCR).
When a TCNT countdown results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the countdown continues from that value.
Initial value of TCNT is H'FFFFFFFF.
12.3.5 Input Capture Register_2 (TCPR_2)
TCPR_2 is a read-only 32-bit register used for the input capture function built only into timer 2.
The TCPR_2 setting conditions due to the TCLK pin are controlled by the input capture function
bits (ICPE1/ICPE0 and CKEG1/CKEG0) in TCR_2. When a TCPR_2 setting indication due to the
TCLK pin occurs, the value of TCNT_2 is copied into TCPR_2.
Initial value of TCPR_2 is undefined.
Rev. 2.00, 09/03, page 317 of 690