HD6417705F133V Datasheet, PDF (176/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

6.3.1 Interrupt Priority Level Setting Registers A to H (IPRA to IPRH)
IPRA to IPRH are 16-bit readable/writable registers in which priority levels from 0 to 15 are set
for on-chip peripheral module, and IRQ and PINT interrupts.
Bit
15 to 0
Bit Name
IPR15 to
IPR0
Initial Value R/W
0
R/W
Description
These bits set the priority level for each interrupt
source in 4-bit units. For details, see table 6.2.
Table 6.2 Interrupt Sources and IPRA to IPRH
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
IPRA
IPRB
TMU0
WDT
TMU1
REF
TMU2
Reserved^*
IPRC
IRQ3
IRQ2
IRQ1
IPRD
PINT0 to PINT7 PINT8 to PINT15 IRQ5
IPRE
IPRF
IPRG
IPRH
DMAC
Reserved^*
TPU0
TPU2
SCIF0
Reserved^*
TPU1
TPU3
SCIF2
USB
Reserved^*
Reserved^*
Note: * Always read as 0. The write value should always be 0.
Bits 3 to 0
RTC
Reserved^*
IRQ0
IRQ4
ADC
Reserved^*
Reserved^*
Reserved^*
As shown in table 6.2, on-chip peripheral module, or IRQ or PINT interrupts are assigned to four
4-bit groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3
to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0
(masking is requested); H'F means priority level 15 (the highest level).
Rev. 2.00, 09/03, page 128 of 690