HD6417705F133V Datasheet, PDF (374/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

13.2.3 Compare Match Counter (CMCNT)
CMCNT is a 16-bit register used as an up-counter.
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT
value matches that of CMCOR, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1.
The initial value of CMCNT is H'0000.
13.2.4 Compare Match Constant Register (CMCOR)
CMCOR is a 16-bit register that sets the compare match period with CMCNT.
The initial value of CMCOR is H'FFFF.
13.3 Operation
13.3.1 Period Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT
value matches that of CMCOR, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1. CMCNT begins counting up again from H'0000.
Figure 13.2 shows the compare match counter operation.
CMCNT value
CMCOR
Counter cleared by
CMCOR compare match
H'0000
Time
Figure 13.2 Counter Operation
Rev. 2.00, 09/03, page 326 of 690