HD6417705F133V Datasheet, PDF (375/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

13.3.2 CMCNT Count Timing
One of four clocks (Pφ/4, Pφ/8, Pφ/16, Pφ/64) obtained by dividing the peripheral clock (Pφ) can
be selected by the CKS1 and CKS0 bits in CMCSR. Figure 13.3 shows the timing.
Pφ
Internal clock
CMCNT input
clock
CMCNT
N-1
N
N+1
Figure 13.3 Count Timing
13.3.3 Compare Match Flag Set Timing
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT matching count value is updated to H'0000). Consequently, after CMCOR
and CMCNT match, a compare match signal will not be generated until a CMCNT clock is input.
Figure 13.4 shows the CMF bit set timing.
Pφ
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 13.4 CMF Set Timing
Rev. 2.00, 09/03, page 327 of 690