HD6417705F133V Datasheet, PDF (309/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Address Modes
• Dual Address Mode
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 8.5, data is read to the DMAC from one external memory in a data read cycle, and
then that data is written to the other external memory in a write cycle.
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
First bus cycle
DMAC
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 8.5 Data Flow of Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the
transfer request. DACK can be output in read cycle or write cycle in dual address mode.
Channel control register (CHCR) can specify whether the DACK is output in read cycle or
write cycle.
Figure 8.6 shows an example of DMA transfer timing in dual address mode.
Rev. 2.00, 09/03, page 261 of 690