HD6417705F133V Datasheet, PDF (600/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

22.2.10 Execution Times Break Register (BETR)
BETR is a 16-bit readable/writable register. When the execution-times break condition of channel
B is enabled, this register specifies the number of execution times to make the break. The
maximum number is 2¹² – 1 times. When a break condition is satisfied, it decrements the BETR
value. A break is issued when the break condition is satisfied after BETR becomes H'0001.
Bit
Initial
Bit
Name
Value R/W Description
15 to 
12
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 BET11 to 0
BET0
R/W Number of Execution Times
Note: If the channel B brake condition set to during instruction fetch cycles and any of the
instructions below perform breaks, BETR is not decremented when the first break occurs.
The decremented values are listed below.
Instruction
Value
Decremented
Instruction
Value
Decremented
RTE
4
DMULS.L Rm,Rn
2
DMULU.L Rm,Rn
2
MAC.L @Rm+,@Rn+
2
MAC.W @Rm+,@Rn+
2
MUL.L Rm,Rn
3
AND.B #imm,@(R0,GBR)
3
OR.B #imm,@(R0,GBR)
3
TAS.B @Rn
3
TST.B #imm,@(R0,GBR)
3
XOR.B #imm,@(R0,GBR)
3
LDC Rm,SR
4
LDC Rm,GBR
4
LDC Rm,VBR
4
LDC Rm,SSR
4
LDC Rm,SPC
4
LDC Rm,R0_BANK
4
LDC Rm,R1_BANK
4
LDC Rm,R2_BANK
4
LDC Rm,R3_BANK
4
LDC Rm,R4_BANK
4
LDC Rm,R5_BANK
4
LDC.L @Rm+,SR
6
LDC.L @Rm+,GBR
4
LDC.L @Rm+,VBR
4
LDC.L @Rm+,SSR
4
LDC.L @Rm+,SPC
4
LDC.L @Rm+,R0_BANK
4
LDC.L @Rm+,R1_BANK
4
LDC.L @Rm+,R2_BANK
4
LDC.L @Rm+,R3_BANK
4
LDC.L @Rm+,R4_BANK
4
LDC.L @Rm+,R5_BANK
4
LDC.L @Rm+,R6_BANK
4
LDC.L @Rm+,R7_BANK
4
LDC.L @Rn+,MOD
4
LDC.L @Rn+,RS
4
LDC.L @Rn+,RE
4
LDC Rn,MOD
4
LDC Rn,RS
4
LDC Rn,RE
4
BSR label
2
BSRF Rm
2
JSR @Rm
2
LDC Rm,R6_BANK
4
LDC Rm,R7_BANK
4
Rev. 2.00, 09/03, page 552 of 690