HD6417705F133V Datasheet, PDF (156/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Invalidating an Address Specification: An address specification can be invalidated by accessing
the memory allocation cache and writing a 0 to the entry’s V bit. When the A bit is 1, the tag
address specified by the write data is compared to the tag address within the cache selected by the
entry address. If the tag addresses match, and if the U bit of the entry is set to 1, the entry is
written back and data is written to the specified the V and U bits. If no match is found, no
operation is carried out.
In the following example, the write data is specified in R0 and the address is specified in R1 (32-
kbyte mode).
; R0=H'01100010; Tag address=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
In the following example, an address (32-bit) to be purged is specified in R0.
MOV.L #H'00001FF0, R1 ; 32-kbyte mode, H'00000FF0 in the 16-kbyte mode.
AND R0, R1
; The entry address is fetched.
MOV.L #H'00000008, R2 ;
OR
R1, R2
; The start is set to H'F0 and the A bit to 1.
MOV.L #H'1FFFFC00, R3 ;
AND R0, R3
; The tag address is fetched. U = V = 0.
MOV.L R3, @R2
; Associative purge.
The above operation should be performed using a non-cacheable area.
Reading the Data of a Specific Entry: To read the data field of a specific entry is enabled by the
memory-mapped cache access. The longword indicated in the data field of the data array in figure
4.4 is read into the register. In the example shown below, R0 specifies the address and R1 shows
what is read (32-kbyte mode).
; R0=H'F100 004C; data array access, entry=B'00000100
; Way = 0, longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
4.5 Usage Note
Do note execute the PREF instruction for the area that cannot be accessed using the cache (P2 and
P4 areas).
Rev. 2.00, 09/03, page 108 of 690