HD6417705F133V Datasheet, PDF (169/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

• Remarks
For details on user break controller, refer to section 22, User Break Controller (UBC).
DMA Address Error:
• Conditions
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
3)
• Types
Instruction asynchronous, processing-completion type
• Save address
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
• Exception code
H'5C0
• Remarks
An exception occurs when a DMA transfer is executed while an illegal instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 8, Direct
Memory Access Controller (DMAC).
5.3.3 General Exceptions (MMU Exceptions)
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLP error exception, TLP invalid exception, TLB protection exception,
and initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB error exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 3, Memory Management
Unit (MMU).
TLB Miss Exception:
• Conditions
Comparison of TLB addresses shows no address match.
• Types
Instruction synchronous, re-execution type
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