HD6417705F133V Datasheet, PDF (33/741 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.2 Input/Output Pins......................................................................................................... 568
23.3 Register Descriptions ................................................................................................... 569
23.3.1 Bypass Register (SDBPR)................................................................................ 569
23.3.2 Instruction Register (SDIR) ............................................................................. 569
23.3.3 Boundary Scan Register (SDBSR) ................................................................... 570
23.3.4 ID Register (SDID).......................................................................................... 577
23.4 Operation..................................................................................................................... 578
23.4.1 TAP Controller................................................................................................ 578
23.4.2 Reset Configuration......................................................................................... 579
23.4.3 TDO Output Timing ........................................................................................ 579
23.4.4 UDI Reset ....................................................................................................... 580
23.4.5 UDI Interrupt .................................................................................................. 580
23.5 Boundary Scan............................................................................................................. 581
23.5.1 Supported Instructions ..................................................................................... 581
23.5.2 Points for Attention ......................................................................................... 582
23.6 Usage Notes................................................................................................................. 583
23.7 Advanced User Debugger (AUD)................................................................................. 583
Section 24 List of Registers ........................................................................... 585
24.1 Register Addresses
(by functional module, in order of the corresponding section numbers) ......................... 586
24.2 Register Bits ................................................................................................................ 595
24.3 Register States in Each Operating Mode ....................................................................... 614
Section 25 Electrical Characteristics .............................................................. 623
25.1 Absolute Maximum Ratings......................................................................................... 623
25.2 DC Characteristics ....................................................................................................... 625
25.3 AC Characteristics ....................................................................................................... 630
25.3.1 Clock Timing .................................................................................................. 631
25.3.2 Control Signal Timing ..................................................................................... 636
25.3.3 AC Bus Timing ............................................................................................... 638
25.3.4 Basic Timing................................................................................................... 640
25.3.5 Burst ROM Timing ......................................................................................... 645
25.3.6 Synchronous DRAM Timing ........................................................................... 646
25.3.7 DMAC Signal Timing ..................................................................................... 668
25.3.8 TMU Signal Timing ........................................................................................ 669
25.3.9 RTC Signal Timing ......................................................................................... 670
25.3.10 16-Bit Timer Pulse Unit (TPU) Signal Timing ................................................. 670
25.3.11 SCIF Module Signal Timing............................................................................ 671
25.3.12 USB Module Signal Timing............................................................................. 672
25.3.13 USB Transceiver Timing ................................................................................. 673
25.3.14 Port Input/Output Timing ................................................................................ 674
25.3.15 UDI Related Pin Timing .................................................................................. 675
Rev. 2.00, 09/03, page xxxi of xlvi